1. Field of the Invention
The invention relates in general to a voltage-regulating device, and more particularly to a voltage-regulating device for charge pump.
2. Description of the Related Art
Charge pumps can be used to increase voltage. Take the writeable flash memory for example: ordinary reading only requires a low voltage, e.g., 3V, whereas writing requires a high voltage, e.g. 12V. While ordinary integrated circuit chips (IC chips) normally have only a power supply of small voltage, e.g. 3V, a charge pump can herein be used to increase the direct current (DC) voltage if a larger-than-3V operating voltage, e.g. 12 V, is needed.
Conventional charge pumps have a number of varieties such as two-phase charge pump, four-phase charge pump, etc. Herein a two-phase charge pump is illustrated for elaboration. Please refer to FIG. 1, a schematic circuit diagram for a conventional two-phase charge pump. Two-phase charge pump 100 includes diodes D1, D2, D3, and D4, capacitors C1, C2, and C3. For the convenience of elaboration, diodes D1, D2, D3, and D4 are assumed to be ideal diodes with zero turn-on voltage. The positive electrode of diode D1 is coupled to DC power supply Vdd while the negative electrode of diode D1 is coupled to node N1 together with the positive electrode of diode D2 and one terminal of capacitor C1, wherein the other terminal of capacitor C1 receives clock signal CLK. The negative electrode of diode D2 is coupled to node N2 together with the positive electrode of diode D3 and one terminal of capacitor C2, wherein the other terminal of capacitor C2 receives inverse clock signal CLK′, inverse of clock signal CLK. The negative electrode of diode D3 is coupled to node N3 together with the positive electrode of diode D4 and one terminal of capacitor C3, wherein the other terminal of capacitor C3 receives clock signal CLK. The negative electrode voltage of diode D4 is exactly the charge pump output voltage Vo.
FIG. 2A is a schematic voltage diagram for the nodes of a charge pump. The voltage for DC power supply Vdd is 3V; the high level and low level voltages for clock signal CLK are 3V and 0V respectively; the initial voltage for node N1 is 3V. When the voltage of clock signal CLK changes to high level, the cross voltage of capacitor C1 still remains at 3V causing V(N1), the voltage of node N1, to be raised to 6V. Similarly, V(N2), the voltage of node N2, is raised to 9V while V(N3), the voltage of node N3, is raised to 12V. Consequently, output voltage Vo is raised to 12V.
FIG. 2B is a schematic output voltage diagram for a conventional charge pump. While the charge pump raises the voltage step by step, output voltage Vo will eventually be raised to 12V. Due to the discharge effect of capacitor C3, however, output voltage Vo starts to drop slightly when the clock signal CLK coupled to capacitor C3 is at low level, but starts to rise up slightly when clock signal CLK is at high level. In worst cases, output voltage Vo will swing for ±1V and result in an undesired ripple-like waveform of the output voltage.